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| INTEGRATED CIRCUITS DATA SHEET PCD5096 Universal codec Preliminary specification File under Integrated Circuits, IC17 1997 Jan 22 Philips Semiconductors Preliminary specification Universal codec CONTENTS 1 2 3 4 5 6 6.1 6.2 6.3 7 7.1 7.2 7.3 8 8.1 8.2 8.3 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 10 11 11.1 11.2 FEATURES GENERAL DESCRIPTION APPLICATIONS ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pin description Pinning Supply concept FUNCTIONAL DESCRIPTION General Clocking Reset and power-down strategy MEMORY AND CONTROL REGISTERS DSP memories Data memory and control register map Control registers organization IOM Features Pin description Functional description Timing IOM control table IOM data buffers Local loop I2C-BUS INTERFACE CODEC TEST LOOPS Test modes definition Codec test loop signal timing 12 12.1 12.2 12.3 13 13.1 13.2 13.3 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 21 PCD5096 APPLICATION INFORMATION Small business systems Large business systems DECT and ISDN APPLICATION EXAMPLES PCD5096 with two active channels Conference call between one PSTN line and two IOM buffers Conference call between two PSTN lines and one IOM buffer LIMITING VALUES HANDLING ELECTRICAL SPECIFICATIONS PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS 1997 Jan 22 2 Philips Semiconductors Preliminary specification Universal codec 1 FEATURES 2 GENERAL DESCRIPTION PCD5096 * Applications in digital terminal equipment featuring line interface and/or voice functions * Digital signal processor performing echo cancellation, codec functions and dial tone detection * Two independent receive and transmit channels * Independent programmable gain for all analog inputs and outputs * Programmable filter correction functions * Flexible configuration of all functions * IOM-2 serial data interface (slave mode only) * Serial data interface to DTAM speech compression ICs * 400 kHz I2C-bus slave interface (four I2C-bus subaddresses) * Codec compatible with G.714 CCITT specification * PCM A-Law/u-Law (G.711 CCITT) and 16-bit linear data * Dual differential inputs and outputs performing the following functions: - Line interface connection - Loudspeaker, speaker phone (hands-free) - Earpiece, microphone (handset) * Peripheral interface: two I/O pins * Separate ringer function * Tone and ringer generator * Conference call * QFP44 package * Low voltage (2.7 to 3.6 V) * Low power consumption. 4 ORDERING INFORMATION TYPE NUMBER PCD5096H The universal codec combines two high resolution bidirectional analog channels with a DSP in a single chip. Besides the analog interfaces the PCD5096 includes two digital interfaces: an I2C-bus interface allowing an external microcontroller to program the chip, and a 4-wire serial interface compatible with IOM-2 and with DTAM speech compression ICs. This programmable serial interface offers up to 14 channels and is capable of handling 8-bit (A-law) or 16-bit (linear PCM) data packages, or any combination of them. It opens the scope for a wide application area, for example in combination with the PCD5093H DECT baseband chip for digital cordless business applications. Several PCD5096s can be connected together for small switching systems (PABX) offering a combination of corded and cordless functionality. Besides the basic functions like echo cancellation for two channels the on-chip DSP provides all necessary functions such as conference call and DTMF. 3 APPLICATIONS The PCD5096 is designed for the telecommunications market and is targeting small business and residential systems offering a two-line interface or a one-line interface combined with hands-free speaker phone. Specific applications are detailed in Chapter 12. PACKAGE NAME QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm VERSION SOT307-2 1997 Jan 22 3 5 handbook, full pagewidth 1997 Jan 22 VDD_2 VSS_2 VDDA_1 VSSA_1 Philips Semiconductors Universal codec BLOCK DIAGRAM system bus 4fs 108fs DAC LIFM_DA1 LIFP_AD1 DIO 1 LIFM_AD1 4fs 108fs ADC AMP1 MICP1 MICM1 VREF1 EARP_HF EARM_HF DIGITAL DECIMATING FILTER LIFP_DA1 DIGITAL NOISE SHAPER A0 I2C-bus A1 SCL INTERFACE SDA DSP CORE CODEC 1 DCL FSC DI IOM BIU DO 108fs DAC 4fs EARP_HS EARM_HS LIFP_AD2 4 DIO 2 XRAM ZROM 4fs 108fs ADC 4K x 24 DIGITAL DECIMATING FILTER 512 x 16 512 x 16 YRAM DIGITAL NOISE SHAPER VDD_1 VSS_1 AMP2 LIFM_AD2 MICP_HS MICM_HS MICP_HF MICM_HF CODEC 2 VMIC_HS VMIC_HF VREF2 SYSTEM DATA RAM (SDR) RESET GENERATOR (RGE) PLL SYSTEM DATA RAM CONTROLLER (SDRC) TCB TIMING CONTROL BLOCK (TICB) 128 WORDS CONTROL REGISTERS ANALOG VOLTAGE REFERENCE MBH864 IO1 VDD_PLL IO0 RESET CLK VSS_PLL TEST VDDA_2 VSSA_2 VBGP Preliminary specification PCD5096 Fig.1 PCD5096 block diagram. Philips Semiconductors Preliminary specification Universal codec 6 6.1 PINNING INFORMATION Pin description QFP44 package PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 I/O(1) I/O I/O I P P P P I I/O I I O O P I I P I I O O O O I I O I I P I I P O O O O I DESCRIPTION programmable I/O pin 0 (Schmitt trigger input, pull-up output) programmable I/O pin 1 (Schmitt trigger input, pull-up output) clock input 3 V analog supply for PLL analog ground supply for PLL peripheral ground supply 3 to 5 V peripheral supply I2C-bus clock signal input (Schmitt trigger) I2C-bus data signal I2C-bus subaddress I2C-bus subaddress negative analog output from Codec 1 to line interface positive analog output from Codec 1 to line interface 3 V analog supply for Codec 1 negative analog input to Codec 1 from line interface positive analog input to Codec 1 from line interface analog ground supply for Codec 1 negative analog input to Codec 1 from microphone positive analog input to Codec 1 from microphone Codec 1 analog reference voltage bandgap analog output voltage Codec 2 analog reference voltage PCD5096 Table 1 SYMBOL IO0 IO1 CLK VDD_PLL VSS_PLL VSS_1 VDD_1 SCL SDA A0 A1 LIFM_DA1 LIFP_DA1 VDDA_1 LIFM_AD1 LIFP_AD1 VSSA_1 MICM1 MICP1 VREF1 VBGP VREF2 VMIC_HS MICP_HS MICM_HS VMIC_HF MICP_HF MICM_HF VSSA_2 LIFP_AD2 LIFM_AD2 VDDA_2 EARP_HS EARM_HS EARP_HF EARM_HF TEST positive analog supply voltage from Codec 2 for handset microphone positive analog input to Codec 2 from handset microphone negative analog input to Codec 2 from handset microphone positive analog supply voltage from Codec 2 for hands-free microphone positive analog input to Codec 2 from hands-free microphone negative analog input to Codec 2 from hands-free microphone analog ground supply for Codec 2 positive analog input to Codec 2 from line interface negative analog input to Codec 2 from line interface 3 V analog supply for Codec 2 positive analog output from Codec 2 to handset earpiece negative analog output from Codec 2 to handset earpiece positive output to hands-free earpiece negative output to hands-free earpiece test input; pull-down 1997 Jan 22 5 Philips Semiconductors Preliminary specification Universal codec PCD5096 SYMBOL RESET VSS_2 VDD_2 DI DO FSC DCL Note PIN 38 39 40 41 42 43 44 I/O(1) I P P I O I/O I/O reset input (Schmitt trigger) digital core ground supply 3 V digital core supply IOM-2 interface serial data input DESCRIPTION IOM-2 interface serial data output (open-drain) IOM-2 interface 8 kHz frame synchronization clock (Schmitt trigger input); note 2 IOM-2 interface data clock (Schmitt trigger input); note 2 1. `P' denotes power line. 2. FSC and DCL are outputs only in test modes. 6.2 Pinning handbook, full pagewidth 34 EARM_HS 36 EARM_HF 35 EARP_HF 38 RESET 40 VDD_2 39 VSS_2 37 TEST 44 DCL 43 FSC 42 DO 41 DI IO0 IO1 CLK VDD_PLL VSS_PLL VSS_1 VDD_1 SCL SDA 1 2 3 4 5 6 7 8 9 33 EARP_HS 32 VDDA_2 31 LIFM_AD2 30 LIFP_AD2 29 VSSA_2 PCD5096 28 MICM_HF 27 MICP_HF 26 VMIC_HF 25 MICM_HS 24 MICP_HS 23 VMIC_HS A0 10 A1 11 LIFM_DA1 12 LIFP_DA1 13 VDDA_1 14 LIFM_AD1 15 LIFP_AD1 16 VSSA_1 17 MICM1 18 MICP1 19 VREF1 20 VBGP 21 VREF2 22 MBH860 Fig.2 Pin configuration. 1997 Jan 22 6 Philips Semiconductors Preliminary specification Universal codec 6.3 Supply concept PCD5096 The universal codec is designed for 3 V systems with a voltage range of 2.7 to 3.6 V. To allow connection to 5 V systems the digital I/Os include level shifters. The core must run on 3.3 V and the peripheral supply on 5 V. The five power supplies are listed in Table 2. Codec 1 and Codec 2 have their own power supplies: VDDA_1 and VDDA_2 respectively. VDD_PLL is the power supply dedicated to the PLL. The digital core and the memories are powered by VDD_2 and the digital peripherals by VDD_1. All digital pins (EARP_HF, EARM_HF, TEST, RESET, DI, DO, FSC, DCL, IO0, IO1, CLK, SCL, SDA, A0 and A1) have internal level shifters, allowing the chip to be used in a 3 to 5 V environment. Table 2 PCD5096 power supply SUPPLY PAIR VDD_1 and VSS_1 VDD_2 and VSS_2 VDD_PLL and VSS_PLL VDDA_1 and VSSA_1 VDDA_2 and VSSA_2 3 to 5 V peripheral supply 3 V digital core supply 3 V PLL supply 3 V Codec 1 supply 3 V Codec 2 supply ASSOCIATED DEVICE handbook, full pagewidth VDD_1 VDD_2 VDD_PLL VDDA_1 VDDA_2 VSS_2 VSS_PLL VSS_1 VSSA_1 VSSA_2 MBH862 Fig.3 PCx5096 supply rails with protection diodes. 1997 Jan 22 7 Philips Semiconductors Preliminary specification Universal codec PCD5096 VDD_2 substrate ring GND5 ring GND ring VDD5 ring VDD ring handbook, full pagewidth VSS_2 substrate ring VSSA2 ring VDDA2 ring 1 VDDA_2 VDD_PLL VSS_PLL VSS_1 VDD_1 PLL DIGITAL CODEC 2 VSSA_2 CODEC 1 VDDA1 ring VSSA1 ring substrate ring MBH861 VDDA_1 Fig.4 PCD5096 power supply. 1997 Jan 22 8 VSSA_1 Philips Semiconductors Preliminary specification Universal codec PCD5096 handbook, full pagewidth 34 EARM_HS 36 EARM_HF 35 EARP_HF 38 RESET 40 VDD_2 39 VSS_2 37 TEST 43 FSC 44 DCL 42 DO 41 DI IO0 1 33 EARP_HS 32 VDDA_2 31 LIFM_AD2 IO1 2 CLK 3 VDD_PLL VSS_PLL VSS_1 VDD_1 SCL 4 30 LIFP_AD2 29 VSSA_2 5 6 PCD5096 28 MICM_HF 7 27 MICP_HF 8 26 VMIC_HF SDA 9 25 MICM_HS A0 10 24 MICP_HS A1 11 23 VMIC_HS LIFM_DA1 12 LIFP_DA1 13 VDDA_1 14 LIFM_AD1 15 LIFP_AD1 16 VSSA_1 17 MICM1 18 MICP1 19 VREF1 20 VBGP 21 VREF2 22 MBH863 Fig.5 Open/short diagram. 1997 Jan 22 9 Philips Semiconductors Preliminary specification Universal codec 7 7.1 FUNCTIONAL DESCRIPTION General PCD5096 The PCD5096 has two general purpose programmable I/O pins controlled by two special registers (direction and state). These two special registers are accessible via the I2C-bus interface or by the on-chip DSP. A typical application is the generation of interrupts by the DSP, indicating that DTMF tones were detected. The timing for the whole chip is generated in the Timing Control Block (TICB). The system clock (20.736 MHz) is delivered by a PLL which triples the input clock frequency. 7.2 Clocking The PCD5096 is a universal codec designed for use in digital terminal equipment. It connects two PSTN lines to a digital interface (IOM-2), thus covering a wide application area. Echo cancellation is performed on both PSTN lines by an on-chip DSP. Hands-free speaker phone functionality is also provided by sacrificing one PSTN line connection. The chip is controlled by an external microcontroller via a high bit rate I2C-bus interface. Figure 1 shows the block diagram of the PCD5096. The different functional blocks operate more or less autonomously and communicate with each other via the System Data RAM (SDR). Each block has access to the SDR via an internal system bus. Access to this bus is controlled by the System Data RAM Controller (SDRC). The IOM block connects to a n x 256 kbits/s digital interface (IOM-2 interface) and also supports interfacing to DTAM speech compression ICs. The IOM block stores and fetches speech data into/from the SDR using internal addressing logic. The DSP block is the link between the data in the SDR stored/fetched by the IOM block on one hand, and the analog front-end on the other hand. The basic functions of the DSP are data filtering, local echo cancelling, network echo suppressing, A-law coding and decoding according to the G.711 CCITT recommendations, dial tone detection and generation, DTMF generation, side-tone, automatic volume control, automatic gain control, double talk detection and conference call. Data processed by the DSP goes to and comes from two independent codecs interfacing to the PSTN lines. The codecs comply with the G.714 specifications and handle the PCM coding and decoding of speech signals. They perform the analog and high speed digital speech processing functions: analog bitstream A/D and D/A conversion, analog filtering and amplification, digital decimation filtering and noise shaping. Both codecs should be connected to a local line or to a PSTN line, but one codec also supports a corded handset and hands-free speaker and microphone. The control of the entire chip is done via the I2C-bus block by writing to the SDR or to special control registers. In this way the DSP and the IOM operation modes can be set, as well as some analog parameters in the two codecs. The universal codec is designed to operate in a digital cordless telephone system, for example together with a PCD5093 baseband controller. To save the expense of having to provide each universal codec with a separate crystal, a common clock is provided by the master controller. In the current generation of the Philips DECT baseband controllers this clock is GP_CLK7, a 6.912 MHz clock output derived from the 13.824 MHz crystal oscillator. GP_CLK7 must therefore be used as the input clock for the universal codec. GP_CLK7 is enabled during a reset of the PCD5093 and when either the Burst Mode Logic or codec are turned on (see PCD5093 data sheet). In order to meet the DSP processing requirements for the various applications an on-chip PLL is used to generate a system clock which is triple the input clock frequency (20.736 MHz). 7.3 Reset and power-down strategy The universal codec must be reset at power-up. The RESET input must remain HIGH until the CLK input is active (toggling) and stable. After releasing the RESET input, an additional 1024 CLK periods (150 s at 6.912 MHz) must elapse before starting to program the chip via the I2C-bus interface. This must be done after every RESET pulse. The minimum duration of a RESET pulse is one CLK period. During reset, the I2C-bus and the IOM-2 interface are inactive. Entering the Power-down mode is achieved by resetting the chip and holding the RESET input HIGH. This resets the on-chip PLL and stops the system clock. The user must ensure that the IOM-2 interface is deactivated and the I2C-bus idle before resetting the chip in order not to interrupt any transaction on these two interfaces. Note that stopping the CLK input is only allowed while the RESET input is HIGH. To exit the Power-down mode the RESET input is set LOW and after 1024 CLK periods (150 s at 6.912 MHz) have elapsed normal operation can be resumed. 1997 Jan 22 10 Philips Semiconductors Preliminary specification Universal codec After reset, all the flip-flops are in a defined state, and the IOM, DSP and codecs are in inactive mode. In typical applications the universal codec is used with the PCD5093, which provides a clock (GP_CLK7) and a reset signal to the universal codec. The reset signal must be generated by a microcontroller port bit. The RESET_OUT pin of the PCD5093 cannot be used for this purpose, because GP_CLK7 is stopped while RESET_OUT is LOW after a Power-on-reset. 8 8.1 MEMORY AND CONTROL REGISTERS DSP memories PCD5096 The memory map is shown in Fig.6. The lower 32 words contain the DSP parameter table. The next 32 words are reserved for the IOM control table, which is used to control the activity on the IOM-2 interface (maximum 32 slots per 8 kHz speech frame). The rest of the SDR addressable space (40H to 77H) is free RAM and can be used to store up to 14 IOM data buffer pairs. In cases where not all 14 IOM buffer pairs are needed this memory space can be used for other applications via the I2C-bus. The same holds for the unused part of the IOM control table. The upper addresses of the SDR (78H to 7EH) are mapped onto 7 control registers (CR0 to CR6) that control the entire chip (DSP mode, data rate on the IOM-2 interface, control of the two codecs). Note that the uppermost address of the SDR (7FH) is not mapped to any hardware register and is addressable as a normal RAM word. The contents of the IOM control table and the IOM data buffers are described in Chapter 9. For further details about the DSP parameter table, see the "PCD5096 DSP user manual". The DSP in the PCD5096 has access to a 4k x 24-bit DSP program ROM, a 512 x 16-bit XRAM and a 512 x 16-bit YRAM. 8.2 Data memory and control register map The PCD5096 contains a 128 word (128 x 16-bit) System Data RAM (SDR) and a group of 7 control registers mapped onto the upper addresses of the SDR. The registers and the SDR are byte and word accessible externally, via the I2C-bus interface and internally via the internal system bus. handbook, full pagewidth 7FH 7EH 78H 77H free RAM control registers (7 words) SDR hardware registers IOM data buffers and free RAM (14 x 4 words) 40H 3FH IOM control table (32 words) 20H 1FH DSP parameter table (32 words) 00H MBH865 SDR Fig.6 PCD5096 Memory map. 1997 Jan 22 11 Philips Semiconductors Preliminary specification Universal codec 8.3 8.3.1 Control registers organization CONTROL REGISTER ASSIGNMENT PCD5096 The control register address assignment in the PCD5096 is shown in Table 3. Table 3 Control register map REGISTER MNEMONIC CR0 SIZE (BITS) 16 ADDRESS (HEX) 78 RESET STATE (HEX) 0000 FUNCTION control signals for codecs, codec test modes, Power-down control and disable phase correction IOM control gain setting of analog-to-digital (A/D) and digital-to-analog (D/A) paths reference voltage setting of Codec 1 and Codec 2 selection of the DSP modes control of I/O pin IO0 control of I/O pin IO1 REGISTER Control Register 0 Control Register 1 Control Register 2 Control Register 3 Control Register 4 Control Register 5 Control Register 6 CR1 CR2 CR3 CR4 CR5 CR6 3 16 16 16 2 2 79 7A 7B 7C 7D 7E 00 0000 A0A0 0000 02 02 1997 Jan 22 12 Philips Semiconductors Preliminary specification Universal codec 8.3.2 Table 4 15 - Table 5 7 HFMICON Table 6 BIT 15 14 13 12 11 10 9 8 7 - DISPC CDC2TM2 CDC2TM1 CDC2TM0 CDC1TM2 CDC1TM1 CDC1TM0 HFMICON CONTROL REGISTER 0 (CR0) Control Register 0 (address 78H) 14 DISPC 13 CDC2TM2 12 CDC2TM1 11 CDC2TM0 10 CDC1TM2 9 PCD5096 8 CDC1TM0 CDC1TM1 Control Register 0 (continued) 6 HSMICON 5 LHFEN 4 EHSEN 3 CDC2ON 2 ADD_DC 1 LIF1_EN 0 CDC1ON Description of CR0 bits SYMBOL reserved, not used Disable Phase Correction. If DISPC = 1, phase correction is disabled. Functional test modes of Codec 2. These 3 bits select the functional test modes of Codec 2; see Table 7. DESCRIPTION Functional test modes of Codec 1. These 3 bits select the functional test modes of Codec 1; see Table 7. Hands-free Microphone ON in Codec 2. When this bit is set the internal microphone reference voltage VREFMIC is connected to pad VMIC_HF (supply pad for the external hands-free microphone). Handset Microphone ON in Codec 2. When this bit is set the internal microphone reference voltage VREFMIC is connected to pad VMIC_HS (supply pad for the external handset microphone). Loudspeaker Enable for hands-free. This bit enables the Noise Shaper data in Codec 2 to the hands-free pads EARP_HF and EARM_HF. Earpiece Enable for Handset. This bit enables the Noise Shaper data to the DAC in Codec 2. Codec 2 ON. When CDC2ON = 1, Codec 2 is ON. Add a DC offset in the microphone amplifier of Codec 1. Line Interface Enable for Codec 1. This bit enables the Noise Shaper data to the DAC in Codec 1. Codec 1 ON. When CDC1ON = 1, Codec 1 is ON. 6 HSMICON 5 4 3 2 1 0 LHFEN EHSEN CDC2ON ADD_DAC LIF1_EN CDC1ON 1997 Jan 22 13 Philips Semiconductors Preliminary specification Universal codec Table 7 Selection of functional test modes for Codec 1 and Codec 2 CDC2TM1 CDC1TM1 0 0 1 1 0 0 1 1 CDC2TM0 FUNCTIONAL TEST MODE CDC1TM2 0 0 0 0 1 1 1 1 8.3.3 Table 8 2 IOM2 Table 9 BIT 2 1 0 CDC1TM0 0 1 0 1 0 1 0 1 normal operation 1 bit analog 1 bit digital 1 bit closed loop 4fs codec 4fs DSP 4fs closed loop PCM probe PCD5096 CDC2TM2 CONTROL REGISTER 1 (CR1) Control Register 1 (address 79H) 1 IOM1 0 IOM0 Description of CR1 bits SYMBOL IOM2 IOM1 IOM0 DESCRIPTION These 3 bits select the IOM mode; see Table 10. Table 10 Selection of IOM mode IOM2 0 0 0 0 1 1 1 1 Note 1. The SpeechPro mode is similar to the IOM slave 32 slots mode, but with a non-doubled data clock DCL. IOM1 0 0 1 1 0 0 1 1 IOM0 0 1 0 1 0 1 0 1 inactive not used IOM slave 256 kbits/s in 4 speech-slots/speech-frame IOM slave 512 kbits/s in 8 speech-slots/speech-frame IOM slave 768 kbits/s in 12 speech-slots/speech-frame IOM slave 1024 kbits/s in 16 speech-slots/speech-frame SpeechPro slave 2048 kbits/s in 32 speech-slots/speech-frame; note 1 IOM slave 2048 kbits/s in 32 speech-slots/speech-frame IOM MODE 1997 Jan 22 14 Philips Semiconductors Preliminary specification Universal codec 8.3.4 CONTROL REGISTER 2 (CR2) PCD5096 CR2 contains the gain setting values of the analog Codec 1 and Codec 2 section. The state of CR2 after reset is 0000H. This sets the A/D path and the D/A path gain to their minimum values of +9 dB and -13 dB respectively. The D/A path gain is defined as the relationship between the level of the analog output signal, differentially seen at EARP_HS - EARM_HS or LIFP_DA1 - LIFM_DA1, expressed in dBm (0 dBm0 is 1 mW in 600 ), and the level of the digital input signal at the PCM interface, expressed in dBm0 according to CCITT Recommendation G.711. This D/A path gain definition assumes that the volume control in the DSP is set to the default value of 0 dB. The A/D path gain is defined as the relationship between the level of the digital output signal at the PCM interface, expressed in dBm0, and the level of the analog input signal at the LIF interface, differentially seen at LIFP_AD2 - LIFM_AD2 or LIFP_AD1 - LIFM_AD1, expressed in dBm. Table 11 Control Register 2 (address 7AH) 15 DA2.3 14 DA2.2 13 DA2.1 12 DA2.0 11 AD2.3 10 AD2.2 9 AD2.1 8 AD2.0 Table 12 Control Register 2 (continued) 7 DA1.3 6 DA1.2 5 DA1.1 4 DA1.0 3 AD1.3 2 AD1.2 1 AD1.1 0 AD1.0 Table 13 Description of CR2 bits BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SYMBOL DA2.3 DA2.2 DA2.1 DA2.0 AD2.3 AD2.2 AD2.1 AD2.0 DA1.3 DA1.2 DA1.1 DA1.0 AD1.3 AD1.2 AD1.1 AD1.0 These 4 bits select the A/D path gain for Codec 1; see Table 15. These 4 bits select the D/A path gain for Codec 1; see Table 14. These 4 bits select the A/D path gain for Codec 2; see Table 15. DESCRIPTION These 4 bits select the D/A path gain for Codec 2; see Table 14. 1997 Jan 22 15 Philips Semiconductors Preliminary specification Universal codec Table 14 Selection of D/A path gain for Codec 1 and Codec 2 DA1.3 DA2.3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DA1.2 DA2.2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DA1.1 DA2.1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DA1.0 DA2.0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D/A PATH GAIN (dB) -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 +1 +2 PCD5096 Table 15 Selection of A/D path gain for Codec 1 and Codec 2 AD1.3 AD2.3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 AD1.2 AD2.2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 AD1.1 AD2.1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 AD1.0 AD2.0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A/D PATH GAIN (FROM LIF TO PCM) (dB) +9 +10 +11 +12 +13 +14 +15 +16 +17 +18 +19 +20 +21 +22 +23 +24 1997 Jan 22 16 Philips Semiconductors Preliminary specification Universal codec 8.3.5 CONTROL REGISTER 3 (CR3) PCD5096 This 16-bit register is used to adjust the reference voltage of Codec 1 and Codec 2 to 2000 mV. An accuracy of 12 mV is guaranteed. The equation for determining the reference voltage (VREFn) for each codec is given below: 256 x VBGP VREFn = --------------------------------RVnREF Where `n' is the codec number and can take a value of `1' or `2'. The default value for VBGP is 1.25 V but this may vary due to process spread (see Chapter 16). Note that increasing RVnREF reduces VREFn. For correct function of the analog blocks, care must be taken to have sensible values in CR3. For example, bits (15:14), as well as (7:6) must be `10'. The state of this register after reset is A0A0H. Table 16 Control Register 3 (address 78H) 15 1 14 0 13 RV2REF5 12 RV2REF4 11 RV2REF3 10 RV2REF2 9 RV2REF1 8 RV2REF0 Table 17 Control Register 3 (continued) 7 1 6 0 5 RV1REF5 4 RV1REF4 3 RV1REF3 2 RV1REF2 1 RV1REF1 0 RV1REF0 Table 18 Description of CR2 bits BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SYMBOL - - RV2REF5 RV2REF4 RV2REF3 RV2REF2 RV2REF1 RV2REF0 - - RV1REF5 RV1REF4 RV1REF3 RV1REF2 RV1REF1 RV1REF0 This bit must be set to a logic 1. This bit must be set to a logic 0. These 5 bits are used to select the reference voltage of Codec 1. This bit must be set to a logic 1. This bit must be set to a logic 0. These 5 bits are used to select the reference voltage of Codec 2. DESCRIPTION 1997 Jan 22 17 Philips Semiconductors Preliminary specification Universal codec 8.3.6 CONTROL REGISTER 4 (CR4) PCD5096 CR4 is used to select the DSP modes. For further information see the "PCD5096 DSP user manual". Its state after reset is 0000H. Table 19 Control Register 4 (address 7CH) 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 LLb2 6 LLb1 5 LLb0 4 LLa2 3 LLa1 2 LLa0 1 OPM1 0 OPM0 Table 20 Description of CR4 bits BIT 15 to 8 7 6 5 4 3 2 1 0 SYMBOL - LLb2 LLb1 LLb0 LLa2 LLa1 LLa0 OPM1 OPM0 These 2 bits select the operation mode, see Table 22. These 3 bits select the connection mode for channel LLa; see Table 21. These 8 bits are not used. These 3 bits select the connection mode for channel LLb; see Table 21. DESCRIPTION Table 21 Selection of the connection mode for channels LLb and LLa LLb2 LLa2 0 0 0 0 1 1 1 1 LLb1 LLa1 0 0 1 1 0 0 1 1 LLb0 CONNECTION MODES LLa0 0 1 0 1 0 1 0 1 Idle mode with reset of LEC coefficients Idle mode without reset of LEC coefficients speech and tone tone generation dial tone detection not allowed not allowed not allowed Table 22 Selection of the operation mode OPM1 0 0 1 1 OPM0 0 1 0 1 connection mode read/write RAM mode software reset not allowed OPERATION MODE 1997 Jan 22 18 Philips Semiconductors Preliminary specification Universal codec 8.3.7 CONTROL REGISTER 5 (CR5) PCD5096 CR5 controls the general purpose I/O pin IO0. Table 23 Control Register 5 (address 7DH) 1 IODIR0 Table 24 Description of CR5 bits BIT 1 0 Note 1. Depending on the DSP program, the contents of CR5 might be overwritten by the DSP as soon as the reset is inactive. 8.3.8 CONTROL REGISTER 6 (CR6) SYMBOL IODIR0 IO0 DESCRIPTION Direction control for IO0. If IODIR0 = 1, then IO0 is an input. If IODIR0 = 0, then IO0 is an output. Input during and after reset; see note 1. State of IO0 0 IO0 CR6 controls the general purpose I/O pin IO1. Table 25 Control Register 6 (address 7EH) 1 IODIR1 Table 26 Description of CR6 bits BIT 1 0 Note 1. Depending on the DSP program, the contents CR6 might be overwritten by the DSP as soon as the reset is inactive. SYMBOL IODIR1 IO1 DESCRIPTION Direction control for IO1. If IODIR1 = 1, then IO1 is an input. If IODIR1 = 0, then IO1 is an output. Input during and after reset; see note 1. State of IO1 0 IO1 1997 Jan 22 19 Philips Semiconductors Preliminary specification Universal codec 9 9.1 IOM Features 9.3 Functional description PCD5096 The IOM block in the PCD5096 is a 4-wire serial interface performing the following functions: * Digital interface with up to fourteen 64 kbits/s channels at a bit rate of n x 256 kbits/s (n = 1, 2, 3, 4 or 8), complying with the IOM-2 specifications (IOM-2 is a registered trademark of Siemens AG) * Digital interface with 32 slots/frame and non-doubled data clock, compatible with the digital interface of some DTAM speech compression ICs * Autonomous storing/fetching of data to/from the system data memory (SDR) using internal addressing logic * Byte or word (16 bits) transfer * 14 data buffers (byte or word) * Muting of speech data * Local call. 9.2 Pin description The digital interface of the PCD5096 can work at several bit rates; these are specified Table 27. The bit rate is selected by writing the appropriate 3 bit code, given in Table 27, into Control Register 1 (address 79H). The PCD5096 is always a slave on the IOM interface, which means that both FSC and DCL are inputs. This is valid for both the IOM modes and the Speech mode. FSC is an 8 kHz framing signal for synchronizing data transmission on DI and DO. The rising edge of FSC gives the time reference for the first bit transmitted in the first slot of a speech frame. The number of slots per speech frame depends on the selected data rate. Each slot contains 8 data bits. DCL is a data clock. Its frequency is twice the selected data rate in IOM mode. In Speech mode, the DCL frequency is equal to the data rate (2048 kHz for 2048 kbits/s). DI is the serial data input. Data coming on DI in packets of 8 bits (A-law PCM encoded data) or 16 bits (linear PCM data) is stored temporarily in an IOM data buffer, from where it is processed by the on-chip DSP. On the other hand, data written into the IOM data buffers by the DSP is shifted out on pin DO. There are 14 IOM data buffers, allowing the use of 14 different channels. One channel is 64 kbits/s for A-law PCM encoded data and 128 kbits/s if linear PCM data is transferred, in which case two consecutive slots are used. The Speech mode was implemented to support the codec interface of some speech compression ICs. This mode is very similar to the IOM 32 slots mode, the main difference being the non-doubled data clock. See Section 9.4 for timing information. The following pins are used by the IOM-2 interface: * DI: serial data input with a bit rate of n x 256 kbits/s (n = 1, 2, 3, 4 or 8) * DO: serial data output with a bit rate of n x 256 kbits/s (n = 1, 2, 3, 4 or 8). DO is an open-drain pin, as many devices must be able to write on the same data line in a time-multiplexed mode. Therefore, DO must be externally pulled-up. * FSC: 8 kHz frame synchronization input * DCL: data clock input. Twice the data transmission frequency on DI and DO, except in the non-doubled data clock mode (see Section 9.3). Table 27 IOM modes IOM2 0 0 0 0 1 1 1 1 IOM1 0 0 1 1 0 0 1 1 IOM0 0 1 0 1 0 1 0 1 MODE These codes deactivate the IOM-2 interface and stop all the transactions on the IOM bus. This is the default state after reset. IOM slave mode, 256 kbits/s in 4 slots/speech-frame IOM slave mode, 512 kbits/s in 8 slots/speech-frame IOM slave mode, 768 kbits/s in 12 slots/speech-frame IOM slave mode, 1024 kbits/s in 16 slots/speech-frame Speech mode, 2048 kbits/s in 32 slots/speech-frame. The Speech mode is similar to the IOM slave 32 slots mode, but with a non-doubled data clock DCL. IOM slave mode, 2048 kbits/s in 32 slots/speech-frame 1997 Jan 22 20 Philips Semiconductors Preliminary specification Universal codec 9.4 Timing PCD5096 The timing on the 4-wire interface for the IOM mode is shown in Fig.7 and specified in Table 28. The timing for the Speech mode is shown Fig.8 and specified in Table 29. handbook, full pagewidth DCL FSC DI/DO bit 7 bit 6 bit 5 tr(DCL) DCL tf(DCL) tWH(DCL) FSC td(DCL-FSC) tsu(FSC-DCL) tWH(FSC) td(FSC-DO) DO td(DCL-DO) TDCL tWL(DCL) bit 7 th(DI) bit 7 MBH866 DI tsu(DI-DCL) Fig.7 4-wire interface timing in IOM mode. 1997 Jan 22 21 Philips Semiconductors Preliminary specification Universal codec PCD5096 handbook, full pagewidth tWH(FSC) TDCL FSC DCL DI/DO B7 B6 B5 B4 B3 B2 B1 B0 FSC td(DCL-FSC) tsu(FSC-DCL) tWL(DCL) DCL tWH(DCL) td(DCL-DO) DO B7 tsu(DI-DCL) th(DI) B6 DI B7 MBH867 Fig.8 4-wire interface timing in Speech mode. 1997 Jan 22 22 Philips Semiconductors Preliminary specification Universal codec Table 28 Timing parameters in IOM mode; see Fig.7 SYMBOL tr(DCL) tf(DCL) TDCL tWH(DCL) tWL(DCL) tr(FSC) tf(FSC) td(DCL-FSC) tsu(FSC-DCL) tWH(FSC) td(DLC-DO) td(FSC-DO) tsu(DI-DCL) th(DI) Notes 1. Corresponds to the highest DCL frequency allowed (4.096 MHz) with a 10% margin. 2. CL = 150 pF. Table 29 Timing parameters in Speech mode; see Fig.8 SYMBOL td(DCL-FSC) tsu(FSC-DCL) tWH(FSC) TDCL tWL(DCL) tWH(DCL) td(DCL-DO) tsu(DI-DCL)) th(DI) Notes 1. Corresponds to the DCL frequency (2.048 MHz) with a 10% margin. 2. CL = 150 pF. PARAMETER frame delay time DCL to FSC frame set-up time FSC to DCL frame width HIGH data clock period data clock pulse width LOW data clock pulse width HIGH data delay from clock set-up time DI to DCL data hold time 60 130 440(1) 150 150 - 60 60 MIN. -twL(DCL) 100 - - - - - 100(2) - - data clock rise time data clock fall time data clock period data clock pulse width HIGH data clock pulse width LOW frame sync rise time frame sync fall time frame delay DCL to FSC frame set-up time FSC to DCL frame width HIGH data delay from data clock data delay from frame set-up time DI to DCL data hold time PARAMETER - - 220(1) 80 80 - - -tWL(DCL) 60 130 - - tWH(DCL) 50 MIN. 60 60 - - - 60 60 60 - - 100(2) 150(2) - - PCD5096 MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns MAX. UNIT ns ns ns ns ns ns ns ns ns 1997 Jan 22 23 Philips Semiconductors Preliminary specification Universal codec 9.5 IOM control table PCD5096 The selection of active slots in the IOM-2 interface and the logic connection between an IOM slot and an IOM data buffer is defined in the IOM control table located at addresses 20H to 3FH of the SDR. The IOM control table is `n' words long. The number `n' is the number of slots resulting from the IOM mode selection in Control Register 1. Speech slot 0 is defined by word 0 (address 20H) in the IOM control table, and speech slot `n' by word `n' (address 20H + n). The IOM interface block reads all words in the IOM control table once every speech frame (125 s). In every IOM slot in a speech frame the IOM-2 interface block reads the corresponding word in the IOM control table. The function of the bits within each word is shown in Table 30. Depending on the IOM mode selected, only part of the IOM control table address space is used. The unused space is free for extra IOM data buffers or for other applications. Table 30 Word definition in the IOM control table BIT B15 to B10 B9 B8 B7 B6 B5 B4 to B0 not used Mute. If B9 = 1, data on the DO output is forced to zero regardless of the contents of the IOM data buffer. The input data on DI is not affected. If B9 = 0, then normal operation is selected. Local. If B8 = 1, swap in/out buffers. If B8 = 0, then normal operation is selected. See Section 9.7. Select byte. When byte transfer is selected (B6 = 1); B7 = 1, selects the high byte and B7 = 0 selects the low byte. Byte/word transfer. If B6 = 1, then byte transfer is selected. If B6 = 0, then word transfer is selected and two consecutive slots are activated. Active slot. If B5 = 1, the slot is active. If B5 = 0, the slot is idle. IOM data buffer assigned to the slot. These 4 bits select the locations in SDR where the IOM data buffer will reside. The allowed values are 10000 to 11101; see Table 31. FUNCTION Table 31 IOM data buffers location in SDR IOM BUFFER CODE ADDRESS IN SDR (HEX) B4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 40 to 43 44 to 47 48 to 4B 4C to 4F 50 to 53 54 to 57 58 to 5B 5C to 5F 60 to 63 64 to 67 68 to 6B 6C to 6F 70 to 73 74 to 77 1997 Jan 22 24 Philips Semiconductors Preliminary specification Universal codec 9.6 IOM data buffers PCD5096 The address space 40H to 77H in the SDR is reserved for up to 14 IOM data buffers. These buffers are used to exchange data between the IOM-2 interface and the on-chip DSP. Each IOM data buffer consists of four 16-bit words: two words for storing inbound data and two words for outbound data; this is shown in Fig.9 handbook, full pagewidth SDR (1) n+4 IOM interface DI DO n+2 OUTBOUND n MBH868 INBOUND DSP (1) IOM data buffers location is SDR: n = S x 4 with S = B4 to B0 of the corresponding word in the IOM control table. Fig.9 Data flow between the IOM-2 interface and the DSP. 9.7 Local loop A local call is implemented in order to loop-back data from one codec to another codec and vice-versa, as illustrated in Fig.10. The inbound and outbound buffer are simply swapped. This is done by setting bit 8 in the correct IOM control table word (see Section 9.5). A local call is created by assigning one IOM data buffer to 2 codecs, whereby in one IOM control word bit 8 is set, and in the other IOM control word bit 8 is reset. handbook, full pagewidth even frame DI 0 n 0 odd frame n 0 even frame n 0 DO 0 n 0 n 0 n 0 MBH869 slot 0 (1) slot n (2) (1) Bit 8 is set in slot 0 control word. (2) Bit 8 is reset in slot n control word. Fig.10 Local call switching on the IOM interface. 1997 Jan 22 25 Philips Semiconductors Preliminary specification Universal codec 10 I2C-BUS INTERFACE The PCD5096 is programmed by writing to the control registers (CR0 to CR6) and loading the SDR using the I2C-bus interface. The master on the I2C-bus is either a PCD509x DECT processor or an external microcontroller. The memory map of the PCD5096 is given in Chapter 8. It consists of 128 words (16 bits wide) of system data IOM buffers, IOM control data and DSP parameters) and 7 words (16 bits wide) of control registers mapped at addresses 78H to 7EH. The I2C-bus interface uses word and byte access to the RAM and to the control registers. For byte access the address is not incremented automatically. For word access the address is incremented after two data bytes (low, high byte) in order to be able to fill the memory without a full I2C-bus protocol (start, slave address, stop bits). PCD5096 The protocol is shown in Figs 12 to 15. I2C_BYTE = 1, for byte access and I2C_BYTE = 0, for word access. I2C_BSEL = 1 for selecting the high byte and I2C_BSEL = 0 for selecting the low byte. For control registers with less than 8 bits, there is no difference between word access, high byte access and low byte access. The PCD5096 has two pins (A1 and A0) for programming the slave address. This means that a maximum of four devices can be located on a board without glue logic. The I2C-bus slave address allocated for the PCD5096 is shown in Fig.11. handbook, halfpage A6 0 A5 0 A4 1 A3 1 A2 0 A1 A1 A0 R/W A0 MBH870 Fig.11 PCD5096 I2C-bus slave address. 1997 Jan 22 26 Philips Semiconductors Preliminary specification Universal codec PCD5096 handbook, full pagewidth acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave S slave address 0 A x RAM address A don't care 0/1 1 A data A P R/W I2C_BYTE I2C_BSEL MBH871 Fig.12 I2C-bus write byte. handbook, full pagewidth acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave S slave address 0 A x RAM address A don't care 0 0 A data (low byte) A R/W I2C_BYTE I2C_BSEL acknowledge from slave acknowledge from slave acknowledge from slave data (low byte) A data (high byte) A data (high byte) A P MBH872 auto increment word address Fig.13 I2C-bus write word. 1997 Jan 22 27 Philips Semiconductors Preliminary specification Universal codec PCD5096 handbook, full pagewidth acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave S slave address 0 A x RAM address A don't care 0/1 1 AS slave address 1A R/W I2C_BYTE I2C_BSEL R/W data 1 P MBH873 no acknowledge from master Fig.14 I2C-bus read byte. handbook, full pagewidth acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave S slave address 0 A x RAM address A don't care 0 0 AS slave address 1 A R/W I2C_BYTE I2C_BSEL acknowledge from master acknowledge from master R/W no acknowledge from master data (low byte) A data (high byte) A data (high byte) 1 P MBH874 auto increment word address Fig.15 I2C-bus read word. 1997 Jan 22 28 Philips Semiconductors Preliminary specification Universal codec 11 CODEC TEST LOOPS 11.1 Test modes definition PCD5096 * 4fs DSP: this loop allows evaluation of the DSP software. On TEST_INPUT and TEST_OUTPUT, data can be exchanged with the DSP (16 bits serially, 2's complement, MSB first). * 4fs closed loop: a connection between the parallel output of DDF and the input of DNS is made. The loop data at 4fs can be monitored by shifting out bits serially via TEST_OUTPUT. * PCM probe: this special test loop allows the evaluation of DSP software. The DSP software however, must include a test mode in which any 16-bit data at a sample rate of fs or 8 kHz (normally only present as numbers within the DSP algorithm) is written to the output line that is connected to DNS. While normally the data on this line has a 4fs (32 kHz) sample rate, up to four (interleaved) PCM signals can be monitored via TEST_OUTPUT. Next to these hardware codec test loops there also may be software DSP test loops, depending on the DSP software version. For more information about the DSP software the DSP manuals must be consulted. In all codec test loop modes (except the normal operation mode) the signals lines TEST_INPUT_x and TEST_OUTPUT_x (x = 1 for Codec 1, x = 2 for Codec 2) are mapped onto pins that normally have a different function. Next to these data signals some timing signals (FS4 and CLK3) are presented on pins. Table 33 shows which pins are used in the codec test loop modes. For debug and evaluation purposes some test loops are implemented in the speech codecs. These test loops are activated by setting bits 13 to 8 in Control Register 0; see Table 32. The signal flow in the test loops is shown in Fig.16 and is described as follows: * Normal operation: the codec is not in any of its test loop modes; used for a normal application. * 1 bit analog: this loop is intended for a separate evaluation of the analog parts of the codec. A bitstream interface (108fs) is available. Via TEST_INPUT bitstream data is fed to the DAC and bitstream data from the ADC is present on TEST_OUTPUT. * 1 bit digital: this loop allows the evaluation of DDF and DNS at the 108fs interface. Bitstream data from TEST_INPUT is led to DDF and bitstream data from DNS is available on TEST_OUTPUT. * 1 bit closed loop: a connection between the bitstream output of the ADC and the bitstream input of the DAC is made. The bitstream data is also made available on TEST_OUTPUT. * 4fs codec: the 4fs codec loop gives access to the 4fs interface for evaluation of DDF and DNS. 16-bit input data is serially shifted in (two's complement, MSB first) on TEST_INPUT and the 14 MSBs are used by DNS. On the other side 16 bits DDF output data is serially shifted out on TEST_OUTPUT. Table 32 Selection of functional test modes for Codec 1 and Codec 2 CDC1TM2 CDC2TM2 0 0 0 0 1 1 1 1 CDC1TM1 CDC2TM1 0 0 1 1 0 0 1 1 CDC1TM0 FUNCTIONAL TEST MODE CDC2TM0 0 1 0 1 0 1 0 1 normal operation 1 bit analog 1 bit digital 1 bit closed loop 4fs codec 4fs DSP 4fs closed loop PCM probe 1997 Jan 22 29 Philips Semiconductors Preliminary specification Universal codec PCD5096 handbook, full pagewidth TEST_INPUT_x DNS DSP DDF DAC DSP ADC, AMP DNS DAC DDF ADC, AMP TEST_OUTPUT_x normal operation: 000 TEST_OUTPUT_x 1 bit analog: 001 DNS DSP DDF DAC DSP ADC, AMP DNS DAC DDF ADC, AMP TEST_INPUT_x TEST_OUTPUT_x 1 bit digital: 010 TEST_INPUT_x 1 bit closed loop: 011 TEST_OUTPUT_x DNS DSP DDF DAC DSP ADC, AMP DNS DAC DDF ADC, AMP TEST_OUTPUT_x TEST_INPUT_x 4fs codec: 100 4fs DSP: 101 TEST_OUTPUT_x DNS DSP DDF DAC DSP ADC, AMP DNS DAC DDF ADC, AMP TEST_OUTPUT_x MBH875 4fs closed loop: 110 PCM probe: 110 Fig.16 Speech codec test loops. 1997 Jan 22 30 Philips Semiconductors Preliminary specification Universal codec Table 33 Pin redefinition in Codec test loop mode NORMAL MODE PIN NAME DI DO A1 IO1 DCL IO0 11.2 SIGNAL NAME TEST_INPUT_1 TEST_OUTPUT_1 TEST_INPUT_2 TEST_OUTPUT_2 CLK3 FS4 I/O I O I O O O CODEC TEST LOOP MODE DESCRIPTION PCD5096 108fs bitstream or 4fs serial data input to Codec 1 108fs bitstream or 4fs serial data output from Codec 1 108fs bitstream or 4fs serial data input to Codec 2 108fs bitstream or 4fs serial data output from Codec 2 3456 kHz bit clock signal (4 x 108fs) with 50% duty cycle 32 kHz word synchronization signal (4fs), duty cycle = 12/108 Codec test loop signal timing The TEST_OUTPUT_x signal changes at the falling edge of CLK3, and the signal presented on TEST_INPUT_x is sampled just before the falling edge of CLK3. Note that the 4fs serial PCM data shifted in via TEST_INPUT_x is only used during the next FS4 HIGH period. handbook, full pagewidth CLK3 FS4 FS1 TEST_OUTPUT_x TEST_INPUT_x MBH877 sample moment for 1 bit digital loop mode sample moment for 1 bit analog loop mode Fig.17 Codec test loop signal timing for 108fs 1-bit bitstream signals. 1997 Jan 22 31 Preliminary specification PCD5096 Fig.18 Codec test loop signal timing for 4fs 16-bit serial signals. handbook, full pagewidth 1997 Jan 22 Philips Semiconductors Universal codec 12 periods of CLK3 12 periods of CLK3 CLK3 FS4 32 14 1 0 15 14 1 0 MBH876 FS1 TEST_OUTPUT_x 15 TEST_INPUT_x sample moment is just before the rising edge of CLK3 Philips Semiconductors Preliminary specification Universal codec 12 APPLICATION INFORMATION 12.1 Small business systems PCD5096 The PCD5096 is designed for business and residential phone systems. In combination with a processor like the PCD5093, two simultaneous calls on 2 PSTN lines (Ba, Bb) can be processed. To realize single line systems with hands-free functionality one analog interface port can be connected to a speaker phone and the other to the line interface. A typical small business system consists of a PCD5093 DECT processor with radio interface and a single universal codec (see Fig.19). The possible configurations for speech connections in the universal codec are listed in Table 34. A real hands-free solution can also be implemented by using one PSTN line port and connecting a corded handset, a hands-free microphone and a loudspeaker to the second analog interface port of the universal codec. handbook, full pagewidth PCD5093 PCD5096 Ba 2x PSTN Bb A D A D ECHO CANCELLATION DSP IOM IOM RADIO CIRCUIT I2C I2C PPa, PPb local (speaker phone) MBH857 Fig.19 Small business system. Table 34 Possible speech connections in a small business system SINGLE CONNECTIONS LOCAL Ba LOCAL Bb LOCAL PPa LOCAL PPb Ba PPa Ba PPb Bb PPa Bb PPb DUAL CONNECTIONS (LOCAL Ba) + (Bb PPa) (LOCAL Bb) + (Ba PPa) (LOCAL PPa) + (Ba PPb) (LOCAL PPb) + (Ba PPa) (Ba PPa) + (Bb PPb) (Ba PPb) + (Bb PPa) - - (LOCAL Ba) + (Bb PPb) (LOCAL Bb) + (Ba PPb) (LOCAL PPa) + (Bb PPb) (LOCAL PPb) + (Bb PPa) - - - - 1997 Jan 22 33 Philips Semiconductors Preliminary specification Universal codec 12.2 Large business systems PCD5096 For large business systems, local loop and public access systems, several PCD5096 codecs can be connected together utilizing the serial bus system. A digital cordless base station for large business systems typically consists of a baseband processor, radio interface and a number of universal codecs interfacing to local lines, PSTN lines and to the local corded handset/hands-free interface. A diagram of this configuration is shown in Fig.20. The universal codec can connect to different applications in a typical large business system. They are as follows: 1. PSTN Line Interface 2. Speaker phone with hands-free feature 3. Local Line Interface. In these applications the additional processing required for conference calling is performed either in the host baseband processor, or in the universal codecs. For further details about these three applications consult the "PCD5096 DSP user manual". handbook, full pagewidth PCD5096 A 2x PSTN Fax D A D DSP I2C IOM PCD5096 A D A D DSP I2C I2C IOM IOM HIGH-END SYSTEM PROCESSOR RADIO CIRCUIT PPa, PPb PCD5096 A local lines D A D DSP I2C IOM PCD5096 A local lines D A D DSP I2C IOM DTAM MBH858 Fig.20 Large business system. 1997 Jan 22 34 Philips Semiconductors Preliminary specification Universal codec 12.3 DECT and ISDN PCD5096 The PCD5096 is perfectly suited to extend an ISDN-based DECT base station with analog extension lines. The IOM-2 interface communicates with the S0 interface chip. The host controller can connect via IOM-2 or I2C-bus to the PCD5096. The two analog interfaces of the PCD5096 can either be used to connect to analog phones/Fax machines, or combine hands-free and one analog extension. handbook, full pagewidth ISDN Fax S0 S0 to IOM IOM PCD5093 PCD5096 A D A D DSP I2C I2C IOM IOM RADIO CIRCUIT MBH859 Fig.21 DECT and ISDN. 1997 Jan 22 35 Philips Semiconductors Preliminary specification Universal codec 13 APPLICATION EXAMPLES PCD5096 In this chapter some application examples are given to assist users with the programming of the PCD5096 (DSP parameter settings, control register settings and IOM-2 interface programming). Three examples are considered: a two channel application, a conference call application between one PSTN line and two IOM buffers, and a conference call application between two PSTN lines and one IOM buffer. 13.1 PCD5096 with two active channels A typical application for the PCD5096 is depicted in Fig.22. Two handsets (PPa and PPb) are connected through a PCD5093 and a PCD5096 to two PSTN lines. Tables 35, 36 and 37 show possible settings for the DSP parameters, the IOM control table and the control registers in the PCD5096. Note that the chosen values for the IOM pointers, the volume parameters and the frequency parameters depend on the application. This means that they can differ from the values that are given in this example. handbook, full pagewidth IOM-2 PCD5093 PCD5096 LLa RADIO CIRCUIT LLb a/b PPa, PPb a/b MBH878 Fig.22 Typical PCD5096 application with two channels. 1997 Jan 22 36 Philips Semiconductors Preliminary specification Universal codec Table 35 DSP parameters for two active channels SDR ADDRESS (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 PARAMETER NAME LLa_IOM1 LLa_LSW LLa_LEC LLa_NES LLa_AGC LLa_TXV LLa_ISW LLa_IOM2 LLa_SMU2 LLa_AVR LLa_RXV LLa_PST LLa_TST LLa_TOV1 LLa_TOV2 LLb_IOM1 LLb_LSW LLb_LEC LLb_NES LLb_AGC LLb_TXV LLb_ISW LLb_IOM2 LLb_SMU2 LLb_AVR LLb_RXV LLb_PST LLb_TST LLb_TOV1 LLb_TOV2 VALUE (HEX) 484C FFFF FFFF 2D2D FFFF 2020 0000 4044 0000 0000 2020 0000 0000 4040 4040 7ECE 7E8A 7E37 7DD2 0000 5054 0000 not used 2 x analog line interface (LLx_IOM1 not used) 2 x Local Echo Canceller ON FUNCTION PCD5096 2 x Network Echo Suppressor (9 dB attenuation) 2 x Automatic Gain Control ON 2 x Transmit Volume set to 0 dB 2 x 8-bit A-law PCM data Codec 1 uses IOM buffer at address 40H Codec 2 uses IOM buffer at address 44H 2 x Soft Mute OFF 2 x Automatic Volume Control OFF 2 x Receive Volume set to 0 dB 2 x Site Tone OFF 2 x Tone Site Tone OFF (LLx_TOGx and LLx_TOVx not used) 2 x Tone Volume for Tone 1 set to 0 dB 2 x Tone Volume for Tone 2 set to 0 dB Tone 1 to Codec 1 Tone 2 to Codec 1 Tone 1 to Codec 2 Tone 2 to Codec 2 no conference call (CCa_IOMx not used) not used not used LLa_TOG1 LLa_TOG2 LLb_TOG1 LLb_TOG2 CCa_CNC CCa_IOM3 reserved CCa_IOM4 CCa_SMU3 CCa_SMU4 Table 36 IOM control table for two active channels SDR ADDRESS (HEX) 20 21 22 to 3F PARAMETER NAME slot 0 control slot 1 control slot 2-slot 32 VALUE (HEX) 0070 0071 0000 FUNCTION IOM slot 0 uses buffer at address 40H IOM slot 1 uses buffer at address 44H slots 2 to 32 inactive 1997 Jan 22 37 Philips Semiconductors Preliminary specification Universal codec Table 37 Control registers for two active channels SDR ADDRESS (HEX) 78 79 7A 7B 7C 13.2 PARAMETER NAME codec control IOM control gain settings A/D and D/A paths VREF1, VREF2 settings DSP modes VALUE (HEX) 005B 0004 D0D0 A0A0 0048 FUNCTION Codec 1 ON, Codec 2 ON IOM slave mode, 768 kbits/s PCD5096 A/D gain = +9 dB, D/A gain = 0 dB for both channels default setting for VREF1 and VREF2 both channels run in speech and tone mode Conference call between one PSTN line and two IOM buffers The PCD5096 is able to perform a 3 party conference call. Figure 23 shows a typical configuration, with two handsets in conference call with an PSTN line. Tables 38, 39 and 40 show possible settings for the DSP parameters, the IOM control table and the control registers in the PCD5096. Note that the LLb block of the PCD5096 could be used in parallel to connect a second PSTN line to another IOM buffer. This is not covered in this example. handbook, full pagewidth IOM-2 PCD5093 PCD5096 LLa a/b PPa, PPb RADIO CIRCUIT CCa LLb MBH879 Fig.23 Conference call between one PSTN line and two IOM buffers. 1997 Jan 22 38 Philips Semiconductors Preliminary specification Universal codec Table 38 DSP parameters for conference call between one PSTN line and two IOM buffers SDR ADDRESS (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 PARAMETER NAME LLa_IOM1 LLa_LSW LLa_LEC LLa_NES LLa_AGC LLa_TXV LLa_ISW LLa_IOM2 LLa_SMU2 LLa_AVR LLa_RXV LLa_PST LLa_TST LLa_TOV1 LLa_TOV2 LLb_IOM1 LLb_LSW LLb_LEC LLb_NES LLb_AGC LLb_TXV LLb_ISW LLb_IOM2 LLb_SMU2 LLb_AVR LLb_RXV LLb_PST LLb_TST LLb_TOV1 LLb_TOV2 VALUE (HEX) 5054 FF00 FF00 2D00 FF00 2000 0000 484C 0000 0000 2000 0000 0000 4040 4040 7ECE 7E8A 7E37 7DD2 0900 4044 0000 not used LLa analog line interface (LLx_IOM1 not used) Local Echo Canceller ON in Codec 1 FUNCTION PCD5096 Network Echo Suppressor (9 dB attenuation) in Codec 1 Automatic Gain Control ON in Codec 1 Transmit Volume set to 0 dB in Codec 1 8-bit A-law PCM data not used Soft Mute OFF Automatic Volume Control OFF Receive Volume set to 0 dB in Codec 1 Site Tone OFF Tone Site Tone OFF (LLx_TOGx and LLx_TOVx not used) Tone Volume for Tone 1 set to 0 dB Tone Volume for Tone 2 set to 0 dB Tone 1 to Codec 1 Tone 2 to Codec 1 Tone 1 to Codec 2 Tone 2 to Codec 2 conference call between Codec 1 and Codec 2 IOM buffers (8 bit A-law PCM data) conference call IOM buffer 1 at address 40H conference call IOM buffer 2 at address 44H soft mute off LLa_TOG1 LLa_TOG2 LLb_TOG1 LLb_TOG2 CCa_CNC CCa_IOM3 reserved CCa_IOM4 CCa_SMU3 CCa_SMU4 Table 39 IOM control table for conference call between one PSTN line and two IOM buffers SDR ADDRESS (HEX) 20 21 22 to 3F PARAMETER NAME slot 0 control slot 1 control slot 2 to slot 32 VALUE (HEX) 0070 0071 0000 FUNCTION IOM slot 0 uses buffer at address 40H IOM slot 1 uses buffer at address 44H slots 2 to 32 inactive 1997 Jan 22 39 Philips Semiconductors Preliminary specification Universal codec Table 40 Control registers for conference call between one PSTN line and two IOM buffers SDR ADDRESS (HEX) 78 79 7A 7B 7C 13.3 PARAMETER NAME codec control IOM control gain settings A/D and D/A paths VREF1, VREF2 settings DSP modes VALUE (HEX) 0003 0004 00D0 A0A0 0008 FUNCTION Codec 1 ON, Codec 2 OFF IOM slave mode, 768 kbits/s PCD5096 A/D gain = +9 dB, D/A gain = 0 dB in Codec 1 default setting for VREF1 and VREF2 channel a in speech and tone mode Conference call between two PSTN lines and one IOM buffer Another configuration for conference call is between two PSTN lines and one IOM buffer, as shown in Fig.24. Tables 41, 42 and 43 show possible settings for the DSP parameters, the IOM control table and the control registers in the PCD5096. handbook, full pagewidth IOM-2 PCD5093 PCD5096 LLa a/b RADIO PPa CIRCUIT CCa LLb MBH880 a/b Fig.24 Conference call between two PSTN lines and one IOM buffer. 1997 Jan 22 40 Philips Semiconductors Preliminary specification Universal codec Table 41 DSP parameters for conference call between one IOM buffer and two PSTN lines SDR ADDRESS (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 PARAMETER NAME LLa_IOM1 LLa_LSW LLa_LEC LLa_NES LLa_AGC LLa_TXV LLa_ISW LLa_IOM2 LLa_SMU2 LLa_AVR LLa_RXV LLa_PST LLa_TST LLa_TOV1 LLa_TOV2 LLb_IOM1 LLb_LSW LLb_LEC LLb_NES LLb_AGC LLb_TXV LLb_ISW LLb_IOM2 LLb_SMU2 LLb_AVR LLb_RXV LLb_PST LLb_TST LLb_TOV1 LLb_TOV2 VALUE (HEX) 5054 FFFF FFFF 2D2D FFFF 2020 0000 484C 0000 0000 2020 0000 0000 4040 4040 7ECE 7E8A 7E37 7DD2 0100 4044 0000 not used FUNCTION PCD5096 2 x analog line interface (LLx_IOM1 not used) 2 x Local Echo Canceller ON 2 x Network Echo Suppressor (9 dB attenuation) 2 x Automatic Gain Control ON 2 x Transmit Volume set to 0 dB 2 x 8-bit A-law PCM data not used 2 x Soft Mute OFF 2 x Automatic Volume Control OFF 2 x Receive Volume set to 0 dB 2 x Site Tone OFF 2 x Tone Site Tone OFF (LLx_TOGx and LLx_TOVx not used) 2 x Tone Volume for Tone 1 set to 0 dB 2 x Tone Volume for Tone 2 set to 0 dB Tone 1 to Codec 1 Tone 2 to Codec 1 Tone 1 to Codec 2 Tone 2 to Codec 2 conference call between Codec 1, Codec 2 and one IOM buffer (8 bit A-law PCM data) conference call with IOM buffer at address 40H CCa_IOM4 not used soft mute off LLa_TOG1 LLa_TOG2 LLb_TOG1 LLb_TOG2 CCa_CNC CCa_IOM3 CCa_SMU3 reserved CCa_IOM4 CCa_SMU4 Table 42 IOM control table for conference call between one IOM buffer and two PSTN lines SDR ADDRESS (HEX) 20 21 to 3F PARAMETER NAME slot 0 control slot 1 to slot 32 VALUE (HEX) 0070 0000 FUNCTION IOM slot 0 uses buffer at address 40H slots 1 to 32 inactive 1997 Jan 22 41 Philips Semiconductors Preliminary specification Universal codec Table 43 Control registers for conference call between one IOM buffer and two PSTN lines SDR ADDRESS (HEX) 78 79 7A 7B 7C PARAMETER NAME codec control IOM control gain settings A/D and D/A paths VREF1, VREF2 settings DSP modes VALUE (HEX) 00FB 0004 D0D0 A0A0 0048 FUNCTION PCD5096 Codec 1 ON, Codec 2 ON with hands-free IOM slave mode, 768 kbits/s A/D gain = +9 dB, D/A gain = 0 dB for both channels default setting for VREF1 and VREF2 both channels run in speech and tone mode 14 LIMITING VALUES Limiting values in accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD_1 VDD_2 VDDA_1 VDDA_2 VDD_PLL IDC PARAMETER supply voltage VDD_1 with respect to VSS_1 supply voltage VDD_2 with respect to VSS_2 analog supply voltage VDDA_1 with respect to VSSA_1 analog supply voltage VDDA_2 with respect to VSSA_2 supply voltage VDD_PLL with respect to VSS_PLL DC current through pins supply pins other pins Ptot Tamb Tstg total power dissipation operating ambient temperature storage temperature - - - -25 -65 150 10 500 +70 +150 mA mA mW C C MIN. -0.5 -0.5 -0.5 -0.5 -0.5 MAX. +6.0 +5.0 +5.0 +5.0 +5.0 UNIT V V V V V 15 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. ESD protection according to Human Body Model is guaranteed up to 2 kV. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS Devices"). 1997 Jan 22 42 Philips Semiconductors Preliminary specification Universal codec 16 ELECTRICAL SPECIFICATIONS Table 44 General parameters SYMBOL fclk Tamb VDD_1 IDD_1(act) IDD_1(off) VDD_2 IDD_2(act) IDD_2(off) VDDA_1 IDDA_1(act) IDDA_1(off) VDDA_2 IDDA_2(act) IDDA_2(off) VDD_PLL IDD_PLL(act) IDD_PLL(off) IDD(tot)(off) Notes PARAMETER clock frequency ambient temperature supply voltage active supply current power off supply current supply voltage active supply current power off supply current analog supply voltage active analog supply current power off supply current analog supply voltage active analog supply current power off supply current supply voltage active supply current power off supply current total power off supply current note 1 note 2 note 3 note 4 note 5 note 3 note 4 note 3 note 4 note 3 note 4 note 5 note 3 note 3 CONDITIONS - -25 2.7 - - 2.7 - - 2.7 - 2.7 - 2.7 - - - MIN. TYP. 6.912 +25 3.3 - 0.1 3.3 18 4 3.3 1.5 33 3.3 1.5 2 3.3 0.1 1 40 - PCD5096 MAX. +70 5.5 - - 3.6 28 - 3.6 3 - 3.6 3 - 3.6 1 - 70 UNIT MHz C V mA A V mA A V mA A V mA A V mA A A no load; notes 5 and 6 - no load; notes 5 and 6 - 1. VDD_1 supplies all digital I/Os to ensure 5 V interfacing. VDD_1 may vary over its range independent of the value of VDD_2, VDDA_1, VDDA_2 and VDD_PLL. If VDD_1 is 5.5 V, VDD_2 cannot be lower than 3.0 V. 2. IDD_1(act) is application dependent. 3. Power off at 25 C and 3.3 V, RESET pin HIGH, clock not running. The pins IO0 and IO1 are then inputs and must be kept HIGH (internal pull-ups). 4. VDD_2, VDDA_1, VDDA_2 and VDD_PLL will have the same value. Internally they are NOT connected. 5. Active mode at 25 C and 3.3 V, clock running. DSP parameter table, IOM control table and control registers set according to Section 13.1 (application example with two active channels). A sine wave signal (1031.25 Hz) at a level of -25 dBm is applied to the microphone input of both codecs. DI is tied to DO to simulate activity on the IOM-2 interface. 6. No load on LIFM_DA1, LIFP_DA1, EARM_HS, EARP_HS, VBGP, VREF1, VREF2, VMIC_HS and VMIC_HF. 1997 Jan 22 43 Philips Semiconductors Preliminary specification Universal codec Table 45 Digital I/Os SYMBOL ILI VIH VIL VOH VOL Rpd Rpu to(f) Notes 1. IOH = -8 mA for pins EARM_HF and EARP_HF. IOH = -2 mA for pins IO0 and IO1. 2. IOL = 8 mA for pins EARM_HF, EARP_HF and DO. IOL = 2 mA for pins IO0 and IO1. 3. Pull-down resistor present at pin TEST. Pull-up resistor present at pins IO0 and IO1. 4. For SDA pin, IOL = 3 mA at 5 V, 1 mA at 3.3 V and 0.7 mA at 2.7 V. 5. Output fall time of SDA measured from VIH(min) to VIL(max). Table 46 Analog supplies SYMBOL Vbgp Vref Rvmic Notes PARAMETER bandgap voltage reference voltage microphone supply output resistance CONDITIONS note 1 notes 2 and 3 note 4 1 1.975 - MIN. TYP. 1.2 2.000 75 PARAMETER leakage current input pins HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage equivalent pull-down resistor equivalent pull-up resistor SDA output fall time note 1 notes 2 and 4 note 3 note 3 notes 4 and 5 CONDITIONS - 0.7VDD_1 - 0.8VDD_1 - - - - MIN. - - - - - 50 100 - TYP. 1 - PCD5096 MAX. UNIT A V V V V k k ns 0.3VDD_1 - 0.4 - - 250 MAX. 1.5 2.025 150 UNIT V V 1. VBGP output current is zero. Decoupling capacitance between pins VBGP and VSSA_1 is 100 nF at 25 C. The bandgap has a temperature coefficient between -0.2 and +0.2 mV/ C. 2. Vref stands for VREF1 or VREF2. Vref output current is zero. Decoupling capacitance between VREF1 and VSSA_1, or between VREF2 and VSSA_2 is between 1 F and 100 F, with a 100 nF capacitance in parallel. The voltage is programmed by setting the appropriate value (80H to BFH) for each codec, in Control Register 3. VMIC_HS and VMIC_HF output current is zero (e.g. by setting bits 6 and 7 in Control Register 3 to a logic 0. The output can only source current (i.e. not sink). 3. Pins VMIC_HS and VMIC_HF (called VMIC below) are internally connected to VREF2 via two switches. The VMIC_HS switch is closed by setting the HSMICON bit in Control Register 0 to a logic 1. The VMIC_HF switch is closed by setting the HFMICON bit in Control Register 0 to a logic 1. The VMIC DC output current is 400 A maximum, and VREF2 must be programmed to its typical value. Use a low pass filter (resistor + capacitor) between VMIC and VSSA_2 of 100 + 10 F, with a 100 nF capacitance in parallel. VMIC adjustment can only be done by adjusting VREF2. 4. Valid for both VMIC_HS and VMIC_HF pins. 1997 Jan 22 44 Philips Semiconductors Preliminary specification Universal codec PCD5096 Table 47 Speech codec Vref1 and Vref2 are tuned to 2.0 V. Typical values for the A/D and D/A filter characteristics conform to the G.712 specification. SYMBOL Vi(MIC1) Vi(MIC_HS) Vi(MIC_HF) Ri(MIC1)(dm) Ri(MIC_HS)(dm) PARAMETER MIC input level (Codec 1) handset MIC input level (Codec 2) hands-free MIC input level (Codec 2) MIC input resistance differential mode seen across MICP1 and MICM1 handset MIC input resistance differential mode seen across MICP_HS and MICM_HS hands-free MIC input resistance differential mode seen across MICP_HF and MICM_HF MIC input resistance common mode seen between MICP1 (or MICM1) and VSSA_1 handset MIC input resistance common mode seen between MICP_HS (or MICM_HS) and VSSA_2 hands-free MIC input resistance common mode seen between MICP_HF (or MICM_HF) and VSSA_2 LIF input level (Codec 1) LIF input level (Codec 2) LIF input resistance differential mode seen across LIFP_AD1 and LIFM_AD1 LIF input resistance differential mode seen across LIFP_AD2 and LIFM_AD2 LIF input resistance common mode seen between LIFP_AD1 (or LIFM_AD1) and VSSA_1 input resistance common mode seen between LIFP_AD2 (or LIFM_AD2) and VSSA_2 note 2 note 2 CONDITIONS note 1 note 1 note 1 - - - - - MIN. TYP. - - - 200 200 MAX. -22 -22 -22 - - UNIT dBm dBm dBm k k Ri(MIC_HF)(dm) - 200 - k Ri(MIC1)(cm) - 500 - k Ri(MIC_HS)(cm) - 500 - k Ri(MIC-HF)(cm) - 500 - k Vi(LIF_AD1) Vi(LIF_AD2) Ri(LIF_AD1)(dm) Ri(LIF_AD2)(dm) Ri(LIF_AD1)(cm) - - - - - - - 30 30 15 -6 -6 - - - dBm dBm k k k Ri(LIF_AD2)(cm) - 15 - k 1997 Jan 22 45 Philips Semiconductors Preliminary specification Universal codec PCD5096 SYMBOL F(A/D)(idle) PARAMETER A/D idle channel noise CONDITIONS note 3 note 4 note 4 - 32 40 - 12 MIN. TYP. -85 40 60 500 15 - - - MAX. -72 UNIT dBm0p dBp dBp s dB S/(N + THD)(A/D)(65) A/D signal-to-noise plus total harmonic distortion ratio (-65 dBm input level) S/(N + THD)(A/D)(25) A/D signal-to-noise plus total harmonic distortion ratio (-25 dBm input level) td(g)(A/D) G(MIC1) A/D path group delay Codec 1 MIC gain from MICP1 - MICM1 to LIFP_AD1 LIFM_AD1 Codec 2 handset MIC gain from MICP_HS - MICM_HS to LIFP_AD2 - LIFM_AD2 Codec 2 hands-free MIC gain from MICP_HF - MICM_HF to LIFP_AD2 - LIFM_AD2 gain A/D path from LIF to PCM 18 G(MIC_HS) 12 15 18 dB G(MIC_HF) 12 15 18 dB G(A/D) Gstep(A/D) G(D/A) Gstep(D/A) Vo(D/A) Ro(D/A_1) Ro(D/A_2) F(D/A)(idle) note 5 GAD - 1.5 GAD +0.1 GDA - 1 +0.5 - - - +1.0 GDA +1.0 1350 10 10 -85 40 70 500 GAD + 1.5 dB +1.9 GDA + 1 +1.5 - 20 20 -72 - - - dB dB dB mV dBmp dBp dBp s gain difference between adjacent steps note 6 (A/D path) gain D/A path from PCM to LIF note 7 gain difference between adjacent steps note 6 (D/A path) D/A path output level D/A path output resistance seen between LIFP_DA1 and LIFM_DA1 D/A path output resistance seen between EARP_HS and EARM_HS D/A idle channel noise note 9 note 10 notes 10 and 11 note 8 - 32 40 - S/(N + THD)(D/A)(40) D/A signal-to-noise plus total harmonic distortion ratio (-40 dBm0 input level) S/(N + THD)(D/A)(0) td(g)(D/A) D/A signal-to-noise plus total harmonic distortion ratio (0 dBm0 input level) D/A-path group delay 1997 Jan 22 46 Philips Semiconductors Preliminary specification Universal codec Notes PCD5096 1. A sine wave rms level applied differentially between the microphone pins. The A/D path gain in Control Register 2 is set to +9 dB. For larger input levels the output signal will saturate. 2. A sine wave rms level applied differentially between pins LIFP_ADn and LIFM_ADn (n = 1 for Codec 1; n = 2 for Codec 2). The A/D path gain is set to +9 dB using Control Register 2. For larger input levels the output signal will saturate. 3. Valid for Codec 1 and Codec 2. Control Register 0 = 0003H (Codec 1) or 0018H (Codec 2) and the A/D path gain in Control Register 2 is set to +9 dB. The microphone pins are shorted together. The value is psophometrically weighted. 4. Valid for Codec 1 and Codec 2. Control Register 0 = 0003H (Codec 1) or 0018H (Codec 2) and the A/D path gain in Control Register 2 is set to +9 dB. A sine wave of 1030 Hz is applied between the microphone input pins. The value is psophometrically weighted and includes harmonic distortion. 5. Valid for Codec 1 and Codec 2. GAD is the A/D gain value selected in Control Register 2. The gain is measured at 1030 Hz from the LIF interface (pins LIFP_ADn and LIFM_ADn, where n = 1 for Codec 1 and n = 2 for Codec 2) to the PCM interface. 6. The difference between two adjacent gain settings as specified in Control Register 2. Valid for Codec 1 and Codec 2. 7. Valid for Codec 1 and Codec 2. GDA is the D/A gain value selected in Control Register 2. The gain is measured at 970 Hz, from the PCM interface to the LIF interface (pins LIFP_DA1 and LIFM_DA1, for Codec 1 and pins EARP_HS and EARM_HS for Codec 2). 8. Valid for Codec 1 and Codec 2. Sine wave rms level differentially seen between pins LIFP_DA1 and LIFM_DA1 (Codec 1) or EARP_HS and EARM_HS (Codec 2), with an input signal of 970 Hz and a level of +3.14 dBm0 at the PCM interface. Load resistance is larger than 120 . The D/A path gain in Control Register 2 is set to +2 dB. 9. Valid for Codec 1 and Codec 2. Control Register 0 = 0003H (Codec 1) or 0018H (Codec 2). The D/A path gain in Control Register 2 is set to 0 dB and the DSP is set to idle mode. The value is psophometrically weighted. 10. Valid for Codec 1 and Codec 2. Control Register 0 = 0003H (Codec 1) or 0018H (Codec 2).The D/A path gain in Control Register 2 is set to 0 dB. A sine wave of 970 Hz is applied. The value is psophometrically weighted and includes harmonic distortion. 11. The D/A path is loaded with (150 + 800 F)//100 pF. 1997 Jan 22 47 Philips Semiconductors Preliminary specification Universal codec 17 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm PCD5096 SOT307-2 c y X A 33 34 23 22 ZE e Q E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 A1 (A 3) Lp L e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 Q 0.85 0.75 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-02-04 1997 Jan 22 48 Philips Semiconductors Preliminary specification Universal codec 18 SOLDERING 18.1 Introduction 18.3 Wave soldering PCD5096 There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 18.2 Reflow soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 Repairing soldered joints Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 1997 Jan 22 49 Philips Semiconductors Preliminary specification Universal codec 19 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values PCD5096 This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 20 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 21 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Jan 22 50 Philips Semiconductors Preliminary specification Universal codec NOTES PCD5096 1997 Jan 22 51 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580/xxx France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2870, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997 Internet: http://www.semiconductors.philips.com SCA53 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 437027/1200/01/pp52 Date of release: 1997 Jan 22 Document order number: 9397 750 01475 |
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